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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45V16AB642
16M-WORD BY 64-BIT VirtualChannelTM DYNAMIC RAM MODULE UNBUFFERED TYPE
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Description
The MC-45V16AB642 is a 16,777,216 words by 64 bits VirtualChannel dynamic RAM module on which 8 pieces of
128M VirtualChannel DRAM : PD45V128821 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 16,777,216 words by 64 bits organization
* Clock frequency and access time from CLK
Part number Read Clock
MC-45V16AB642KF-A75
* Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Dual internal banks controlled by BA0 (Bank Select) * Wrap sequence (interleave) * Burst length (4) * Read latency (2)
* Prefetch read latency (4)
* Auto precharge and without auto precharge * Auto refresh and self refresh * Single 3.3 V 0.3 V power supply * Interface: LVTTL * Refresh cycle: 4K cycles/64 ms
* 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Unbuffered type * Serial PD
Document No. E0027N10 (1st edition) (Previous No. M15112EJ2V0DS00) Date Published January 2001 CP (K) Printed in Japan
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latency frequency MHz (MAX.) 2 133
Access time from CLK ns (MAX.)
Maximum supply current mA Operating Prefetch Restore Channel Refresh Auto Self
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
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5.4 1,200
read / write (Burst) 520 1,840 16
This Product became EOL in January, 2003.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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MC-45V16AB642
Ordering Information
Part number Clock frequency MHz (MAX.) MC-45V16AB642KF-A75 133 2 Read latency Prefetch read latency 4 168-pin Dual In-line 8 pieces of PD45V128821G5 Package Mounted devices
Memory Module (Socket Type) (10.16 mm (400) TSOP (II)) Edge connector : Gold plated 34.93 mm height
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MC-45V16AB642
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85 86 87 88 89 90 91 92 93 94 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC VSS NC NC Vcc /WE DQMB0 DQMB1 /CS0 NC VSS A0 A2 A4 A6 A8 A10 A12 Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL Vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
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95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC VSS NC NC Vcc /CAS DQMB4 DQMB5 NC /RAS VSS A1 A3 A5 A7 A9 BA0 (A13) A11 Vcc CLK1 NC VSS CKE0 NC DQMB6 DQMB7 NC Vcc NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc
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A0 - A12
: Address Inputs : VirtualChannel DRAM Bank Select : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable
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BA0 (A13) DQ0 - DQ63 CKE0 /RAS /CAS /WE CLK0 - CLK3 /CS0, /CS2 SA0 - SA2 SDA SCL VCC VSS NC WP
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[Row: A0 - A12, Column: A0 - A7]
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DQMB0 - DQMB7 : Clock Input for PD : Power Supply : Ground : Write Protect : No Connection
: Address Input for EEPROM : Serial Data I/O for PD
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MC-45V16AB642
Block Diagram
/WE /CS0 DQMB0 /CS2 DQMB2
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D0 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
DQMB3
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D2 DQ 3 DQ 2 DQ 1 DQ 0
/WE
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DQMB1
DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQ 7 DQM DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0
/CS
/WE
D1
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
DQMB6
DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D3 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQMB4
Remarks 1. The value of all resistors is 10 except WP. 2. D0 - D7: PD45V128821 (8M words x 8 bits x 2 banks) 4
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DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D4 DQ 3 DQ 2 DQ 1 DQ 0
DQMB5
/WE
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D6 DQ 3 DQ 2 DQ 1 DQ 0
/WE
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DQMB7
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
DQ 5 DQM /CS DQ 7 DQ 6 DQ 4 D5 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D7 DQ 3 DQ 2 DQ 1 DQ 0
/WE
CLK0
CLK : D0, D1, D4, D5 3.3 pF
A0 - A12 BA0
A0 - A12 : D0 - D7
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A13 : D0 - D7 /RAS /RAS : D0 - D7 /CAS /CAS : D0 - D7 CKE : D0 - D7 CKE0 SERIAL PD SDA SCL A0 A1 A2 WP
CLK2
CLK : D2, D3, D6, D7
3.3 pF
CLK1, CLK3
10 pF
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47 k
VCC C VSS
D0 - D7 D0 - D7
SA0 SA1 SA2
MC-45V16AB642
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 8 0 to 70 -55 to +125 Unit V V mA W C C
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Operating ambient temperature Storage temperature
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
Recommended Operating Conditions
Supply voltage High level input voltage Low level input voltage
Operating ambient temperature
Capacitance (TA = 25C, f = 1 MHz)
Parameter Input capacitance
Data input/output capacitance
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Parameter Symbol VCC VIH VIL TA Symbol CI1 CI2 CI3 CI4 CI5 CI/O
permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
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Condition MIN. 3.0 2.0 -0.3 0 Test condition MIN. 38 24 A0 - A12, BA0 (A13), /RAS, /CAS, /WE CLK0, CLK2 CKE0 /CS0, /CS2 DQMB0 - DQMB7 DQ0 - DQ63 32 17 7 7
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TYP. 3.3
MAX. 3.6 VCC + 0.3 +0.8 70
Unit V V V C
TYP.
MAX. 62
Unit pF
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40 52 29 13 13
pF
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MC-45V16AB642
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Operating current (Prefetch mode at one bank active) Operating current (Restore mode at one bank active) Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P CKE VIL (MAX.), tCK = 15 ns CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC2NS CKE VIH (MIN.), tCK = , Input signals are stable. ICC3P CKE VIL (MAX.), tCK = 15 ns 80 48 48 240 mA mA 9.6 9.6 160 mA mA ICC1R Symbol Test condition ICC1P tRC tRC (MIN.) Prefetch is executed one time during tRC. tRC tRC (MIN.) -A75 1,200 mA 1 Grade -A75 MIN.
MAX.
Unit Notes mA 1
1,200
ICC2PS CKE VIL (MAX.), tCK = ICC2N
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Active standby current in power down mode Active standby current in non power down mode Operating current (Burst mode) Auto Refresh current Self refresh current Input leakage current Output leakage current High level output voltage Low level output voltage
ICC3PS CKE VIL (MAX.), tCK = ICC3N CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC3NS CKE VIH (MIN.), tCK = , Input signals are stable. ICC4 tCK tCK (MIN.), IO = 0 mA -A75
160 520 mA 2
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
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ICC5 ICC6 II (L) IO (L) VOH VOL tRCF tRCF
Background : precharge standby
(MIN.)
-A75 -A75 -8 -1.5 2.4
1,840 16 +8 +1.5
mA mA
3
CKE 0.2 V
VI = 0 to 3.6 V, All other pins not under test = 0 V DOUT is disabled, VO = 0 to 3.6 V IO = - 4.0 mA
A A
V
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IO = + 4.0 mA
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MC-45V16AB642
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). * An access time is measured at 1.4 V.
tCK tCH tCL tCK tCL
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CLK CKE Command Address DQM (Input) Data (Input) Data (Output)
tCKS
tCKH
tS
tH
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Valid tAC tLZ Hi-Z
tDS
tDH
tDS
tDH
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Valid tAC tOH Valid
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Valid
tHZ Hi-Z
Valid
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AC characteristics
Parameter Symbol MIN. Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time tCK2 tAC2 tCH tCL tOH tLZ tHZ2 tDS tDH tS tH tCKS tCKH tCKSP tT tREF tRSC 7.5 - 2.5 2.5 2.7 0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.5 - 2 -A75 MAX. - 5.4 - - - - 5.4 - - - - - - - 30 64 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms CLK 1 1 Unit Note
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Data-out low-impedance time Data-out high-impedance time Data-in setup time Data-in hold time CKE setup time CKE hold time Transition time Mode register set cycle time
Address, Command, DQM setup time Address, Command, DQM hold time
CKE setup time (Power down exit)
Refresh time (4,096 refresh cycle)
Note 1. Output load.
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Output
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MC-45V16AB642
AC characteristics (Background to Background operation)
Parameter Symbol MIN. 6DPH %DQN 2SHUDWLRQ ACT to ACT / REF Command period REF to REF / ACT Command period ACT to PRE Command period PRE to ACT / REF Command period ACT to PFC / PFCA Command delay time ACT to PFR Command delay time (Prefetch Read Operation) PFC to PRE Command delay time PFCA / PFR to ACT / REF Command delay time RST / RSTA to ACT(R) Note1 Command delay time tRC tRCF tRAS tRP tAPD tAPRD tPPL tPAL tRAD 67.5 67.5 52.5 20 15 15 22.5 45 7.5 - - 120,000 - - - - - 30 ns ns ns ns ns ns ns ns ns 2 -A75 MAX. Unit Notes
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ACT(R)
Note1
6DPH 2WKHU %DQN 2SHUDWLRQ tRPD tPPD 37.5 22.5 - - ns ns
PFC to PFC / PFCA Command delay time
ACT to ACT / ACT(R) or ACT(R) to ACT Command delay time ACT(R) to ACT(R) Command delay time
PFC / PFCA to RST / RSTA Command delay time
Notes 1. ACT (R) command is ACT command after RST command.
2. The another background operation and same channel foreground operation are illegal while tRAD period.
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to PFC / PFCA / PFR Command delay time
tRRD
15
-
ns
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tRRDR tPRD 30 - 22.5 -
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ns
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AC characteristics (Foreground to Foreground operation)
Parameter Symbol -A75 MIN. READ/WRITE to READ/WRITE Command delay time tCCD 7.5 MAX. - ns Unit Note
AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore)
Parameter Symbol -A75 MIN. tPCD tRCD 15 30 MAX. - - ns ns 1 Unit Note
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PFC/PFCA to READ/WRITE Command delay time ACT(R) to READ/WRITE Command delay time
Note 1. ACT (R) command is ACT command after RST command.
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Serial PD
(1/2)
Byte No. 0 Function Described Defines the number of bytes written into serial PD memory 1 Total number of bytes of serial PD memory 2 3 4 5 6 7 8 9 Fundamental memory type 08H 0DH 08H 01H 40H 00H 01H -A75 75H 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 VC DRAM 13 rows 8 columns 1 bank 64 bits 0 LVTTL 7.5 ns 08H 0 0 0 0 1 0 0 0 256 bytes Hex 80H Bit 7 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Notes 128 bytes
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Number of banks Data width cycle time 10 access time 11 12 13 14 15 16 17 18 19 20 21 22 23-26 27 28 29 30 tRP (MIN.) tRRD (MIN.) tAPD (MIN.) tRAS (MIN.) Refresh rate / type VC DRAM width Minimum clock delay
Number of row addresses Number of column addresses
Data width (continued) Voltage interface standard
Read latency (/CAS latency) = 2
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Read latency (/CAS latency) = 2 -A75 DIMM configuration type Error checking DRAM width Burst length supported Number of banks on each VC DRAM Read latency (/CAS latency) supported /CS latency supported /WE latency supported VC DRAM module attributes VC DRAM device attributes : general -A75 -A75 -A75 -A75
54H
0
1
0
1
0
1
0
0
5.4 ns
00H 80H
0 1
0 0
0 0
0 0
0 0
0 0 0
0 0 0 0 0 0 1 1 0 0
0 0 0 0 1 0 0 0 1 1
None Normal x8 None 1 clock 4 2 banks 2 0 0
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08H 0 0 0 0 1 00H 0 0 0 0 0 01H 0 0 0 0 0 04H 0 0 0 0 0 02H 0 0 0 0 0 02H 0 0 0 0 0 01H 0 0 0 0 0 01H 00H 0EH 00H 14H 0FH 0FH 34H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0
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0
0
1 0
0 0 0
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0 0 0 1 1 0 0 0 0 1 0 0 20 ns 1 1 1 15 ns 1 1 1 15 ns 1 0 0 52.5 ns
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MC-45V16AB642
(2/2)
Byte No. 31 32 Function Described Module bank density Address and command signal input setup time 33 Address and command signal input hold time 34 35 36 Data signal input setup time Data signal input hold time -A75 -A75 -A75 -A75 15H 08H 04H 0FH 02H 04H 08H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 1.5 ns 0.8 ns 4 clocks 15 ns 2 bits 16 256 bits -A75 08H 0 0 0 0 1 0 0 0 0.8 ns -A75 Hex 20H 15H Bit 7 0 0 Bit 6 0 0 Bit 5 1 0 Bit 4 0 1 Bit 3 0 0 Bit 2 0 1 Bit 1 0 0 Bit 0 0 1 Notes 128M bytes 1.5 ns
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Prefetch read latency tPCD (MIN.) 37 38 39 40 Number of channels Depth of channels 41-61 62 63 SPD revision 64-71 72 73-90 91-92 93-94 95-98 99-125 Manufacture's P/N Revision code Manufacturing date Mfg specific
Number of segment addresses
Timing Charts
Please refer to the PD45V128421, 45V128821, 45V128161 Data sheet (E0025N).
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Checksum for bytes 0 - 62 -A75 Manufacture's JEDEC ID code Manufacturing location Assembly serial number
02H 34H
0 0
0 0
0 1
0 1
0 0
0 1
1 0
0 0
2.0
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MC-45V16AB642
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) R2 F1 Q L H K C G D A1 (AREA A)
ITEM A A1 B C D D1 D2 E F1 F2 G H I J K L M M1 M2 N P Q R1 R2 S T U V W X Y1 MILLIMETERS 133.35 133.350.13 11.43 36.83 6.35 2.0 3.125 54.61 2.44 3.18 6.35 1.27 (T.P.) 8.89 24.495 42.18 17.78 34.930.13 15.15 19.78 3.0 MAX. 1.0 R2.0 4.00.10 9.53 3.0 1.270.1 4.0 MIN. 0.20.15 1.00.05 2.540.10 3.0 MIN. 2.26 3.0 MIN. 2.26
Y1 Y2
Z1 Z2
N F2
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R1 A J B I M2 (AREA A) M1 (AREA B)
M
B
S
(OPTIONAL HOLES)
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Edition / Date Page This edition Previous edition NEC Corporation (M15112E) 1st edition / Sep. 2000 2nd edition / Dec. 2000 p.1, 2 p.1, 2 Deletion -A10 -A10 specs - - - - Type of edition Description Location
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Elpida Memory, Inc. (E0027N) 1st edition / Jan. 2001 -
p.6, 8, 9, 10, p.6, 8, 9, 10, 11, 12 11, 12
-
-
Republished by Elpida Memory, Inc.
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MC-45V16AB642
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
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2 3 Note:
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having reset function.
being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices
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The names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company.
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
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* The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. * Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above).
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